When analog video signals such as RGB (red-green-blue) or YUV (luminance-chrominance) video signals of a video/graphics image are displayed on a pixelated display device, graphics digitizers employing analog-to-digital conversion are utilized to convert the analog signals to a digital format. The conversion from an analog to a digital format generally utilizes three analog-to-digital converters (ADCs), which convert, for example, red, green, and blue analog signals to digital signals simultaneously. In analog-to-digital conversion, identifying the correct sampling frequency for the ADCs is essential since even a small error in sampling frequency can impair the resulting displayed images. The phase of the sampling clock for analog-to-digital conversion is also critical since improper selection of phase can also create undesirable visible effects. Thus, when a pixelated display device is driven with analog signals, a circuit is required to automatically search for the correct sampling frequency to produce a high quality image. This is necessary because analog signals are generally produced from signals derived from a clock with frequency and phase that is not perfectly synchronized with the frequency and phase of a local clock controlling the analog-to-digital converters. In addition, a second circuit is generally required to automatically search for the appropriate sampling phase. The sampling phase is the point in time within a sampling clock's cycle for triggering the ADC.
An example of a graphical display device developed for personal computers and television receivers that can utilize a digital video signal is a liquid crystal display (LCD). LCDs offer space savings, lower radiation emission, and lower power consumption compared to cathode-ray tube (CRT) monitors which directly use analog video inputs. Since an analog display interface is still the dominant interface between an image source and a display device, particularly in the personal-computer industry, the use of graphics digitizers to convert analog signals to digital signals has become a vital process for interfacing image sources to digital display devices such as LCDs. Several commercial devices formed as integrated circuits are available to provide analog-to-digital video conversion, such as the Texas Instruments, Inc. THS8083, as described in the THS8083 Data Manual, Texas Instruments Inc, dated April 2001, and the Analog Devices, Inc. AD9884A as described in the AD9884A Data Sheet, Rev. C, Analog Devices, Inc., dated 2001, pp. 1-24. These devices each contain three ADCs that simultaneously convert red, green, and blue analog video signals to corresponding video signals in a digital format.
FIG. 1 illustrates an exemplary block diagram showing the interconnection of signals in a pixelated display system, i.e., a “digitally driven display system” or a “digital display system.” Pixelated display systems are distinguished from analog display systems such as CRTs by displaying images with fixed pixel locations that are formed in the manufacturing process. CRTs can display an image over a continuous surface such as the surface of a CRT, and accordingly are driven directly with analog signals.
In the block diagram illustrated in FIG. 1, video or graphic images are generated inside a video/graphics card 101 such as a video/graphics card in a personal computer. Digital images are converted in this card to analog waveforms by digital-to-analog converters (DACs) such as DAC 105. Digital signals such as RGB signals in a digital format are supplied to the DAC from an external source (not shown). The analog waveforms produced by the digital-to-analog conversion are coupled over line 135 to digital display device 102 such as an LCD display device and converted to a digital format by ADC 115. Control circuitry 110 controls the DAC and produces horizontal and vertical synchronization signals HSYNC and VSYNC that are coupled to the display device over line 140. In the display device, a clock generation circuit 130, usually implemented with a phase-locked loop (PLL), generates a sampling clock signal though a phase control circuit 120 to control the sampling instant of the ADC and display circuitry 125. In such display applications, a key issue for high quality image recovery is thus accurate determination of both the sampling frequency and the sampling phase for the ADCs. These two factors have a dominant impact on the quality of displayed images.
A phase-locked loop 200 such as illustrated in FIG. 2 is commonly used to generate the sampling frequency for the ADCs. When a PLL is locked onto the horizontal synchronization signal (HSYNC), its output is used as the sampling clock for the ADCs. The dividing ratio of the programmable frequency divider 225 is typically programmed to the “number of total pixels per video line” for a given video/graphics mode. Thus, the resulting frequency of the sampling clock is the HSYNC frequency multiplied by the “number of total pixels per video line.” Ideally, by this mechanism, the sampling clock will have the same frequency as that of the pixel clock in the video card. However, this does not occur in practice because the low frequency HSYNC signal is usually noisy and has significant timing jitter. Furthermore, its frequency may not be accurate. In addition, the pixel clock frequency of the video/graphics card might not be equal to the frequency as specified in the Video Electronics Standards Association (VESA) specification, “Generalized Timing Formula Standard,” Version 1.1, Sep. 2, 1999, pp. 1-31. As a result, the original image that is encoded in the analog signals may not be accurately recovered. Thus, a process to determining the sampling frequency is essential in real applications to display high quality images.
In the block diagram illustrated in FIG. 2, PFD 205 is a frequency and phase detector that converts the frequency or phase difference of its two inputs to voltage signals. The voltage-controlled oscillator (VCO) 220 is an oscillator with frequency dependent on an input control voltage. The programmable frequency divider 225 in the feedback loop divides the VCO frequency to a proportionately lower value. The charge pump 210 and the loop filter 215 convert and filter the PFD output to a signal level with noise sufficiently attenuated that it can be utilized as input by the VCO. The output of the VCO (which is the sampling clock of the ADC) is locked to the HSYNC signal through the programmable frequency divider. The dividing ratio of the programmable frequency divider determines the VCO frequency. Ideally, this ratio should be the “number of total pixels per video line” as suggested in the VESA specification. However, the number represented by the “number of total pixels per video line” is not always honored by all the video card vendors and the resulting frequency will not be correct in those cases, again demonstrating that an improved frequency detection process is required to find the correct dividing ratio so that a high quality image can be displayed.
A further uncertainty in producing a high quality image on a digital display device is the typical use of separate electrical paths to couple analog display signals and other timing reference signals from a graphics source to the digital display device. Due to varying cable lengths and impedances, timing reference signals and the analog display signals can be received by the display device at slightly varied times. Thus, deciding when to sample the analog display signals (by adjusting the clock edge within a sampling clock cycle) has substantial impact on the quality of displayed images. The exact point in time of sampling within a cycle of the sampling clock is defined as the sampling phase. The task of determining the appropriate sampling phase could be done manually by a user through visual inspection of displayed images. However, different users may apply different judgments when choosing “good” images. Manual techniques are often cumbersome, even for experienced users, and are thus often impractical and produce variable results.
Eglit, in U.S. Pat. No. 5,847,701 entitled “Method and Apparatus Implemented in a Computer System for Determining the Frequency Used by a Graphics Source for Generating an Analog Display Signal,” dated Dec. 8, 1998, describes searching sampling frequencies using predetermined test patterns. Sequences of test patterns are encoded in an analog video source and transmitted to a digital display device where the analog signal is converted to sequences of sampled values. The digital display device determines whether the sampled values equal one of the sequences of the test patterns based on a predetermined convention. The digital display device changes the sampling frequency until the sampled values equal one of the test pattern sequences, and the corresponding frequency is used as the ADC sampling frequency when a match is found. Thus, Eglit in U.S. Pat. No. 5,847,701 requires predetermined test patterns encoded in an analog video source, which in turn requires additional hardware and software. Unfortunately, display device designers usually do not have control over how the video source is configured and how it is designed. Moreover, the operation uses a feedback system which does not specify how the next sampling frequency should be determined. The scheme just varies the sampling frequency, which poses a convergence timing problem. Thus, using the method described by Eglit, a mechanism is still required to efficiently determine the next sampling frequency and impractical constraints placed thereby on the display device designer are not resolved.
Nakano, in U.S. Pat. No. 6,097,444 entitled “Automatic Image Quality Adjustment Device Adjusting Phase of Sampling Clock for Analog Video Signal to Digital Video Signal Conversion,” dated Aug. 1, 2000, describes choosing the sampling frequency by detecting the HSYNC and VSYNC frequencies and comparing them to the commonly used standard video timing data specified in the VESA guideline referenced above. The VESA mode whose timing data most closely resembles the detected HSYNC and VSYNC frequencies is the desired VESA mode. The corresponding pixel frequency is used as the sampling frequency. However, a problem with this scheme is that the pixel frequency specified in VESA documents is just a guideline. In real applications, significant frequency deviations occur and a degree of frequency error in the pixel clock is unavoidable, the latter of which adversely affects image quality.
Nakano, in U.S. Pat. No. 6,097,444, further discusses a parameter “Value Difference,” which is defined therein as the functionVF[pixel]=|vc−vp|where vc, vp are the RGB values of the current and previous pixel, respectively. The phase-searching method described by Nakano finds the pixel “max pixel” in a frame for which VF[max_pixel] is the maximum. Then the sampling phase is varied for a frame and each phase generates a corresponding VF[max_pixel][phase]. Thus, VF[max_pixel][phase] depends on pixel location and frame sampling phase. The phase that makes VF[max_pixel] [phase] achieve the maximum is the optimal frame sampling phase. The process described by Nakano is based on the assumption that if two adjacent pixels have different RGB values, then among all available phases the optimal frame sampling phase should make their RGB Value-Difference the maximum. However, in this process, only two pixels are used for the calculation, which introduces substantial likelihood of random errors. Moreover, there are usually signal overshoot and undershoot responses if two adjacent pixels have significantly different RGB values, which adds further uncertainty and inaccuracy to the process of maximizing VF[max_pixel] [phase]. Thus, the process described by Nakano may not reliably and consistently produce a high quality image. The process also does not utilize relationship information among different pixel phases.
Eglit, in U.S. Pat. No. 6,268,848 entitled “Method and Apparatus Implemented in an Automatic Sampling Phase Control System for Digital Monitors,” dated Jul. 31, 2001, discusses values of “peak” and “valley” as illustrated in FIG. 3. In this figure, the x-axis represents a sequence of pixels or, equivalently, the progression of time. The y-axis represents the RGB value of a pixel. The peaks and valleys are found by using pixels in a plurality of video lines for a certain sampling phase. Then a statistical value is generated by summing the magnitudes of the peaks and valleys. The phase that maximizes this value is the optimum sampling phase. Compared to the method presented in U.S. Pat. No. 6,097,444, this method may produce a better image because more pixels are used to make the phase selection decision. But this method does not utilize inter-phase relationship information for the calculation. To be precise, FIG. 3 illustrates a waveform of a series of pixels, where at each pixel position there is only one value, which corresponds to one sampling phase, thereby ignoring the inter-phase relationship among all sampling phases before making a phase selection decision, which may often be less than optimal.
Eglit, in U.S. Pat. No. 6,483,447, entitled “Digital Display Unit Which Adjusts the Sampling Phase Dynamically for Accurate Recovery of Pixel Data Encoded in an Analog Display Signal,” dated Nov. 19, 2002, presents a method of searching for the optimal sampling phase by detecting pixels boundaries, or transition points in an analog waveform. Usually the sharp signal transition points, which are required by this method, are accompanied by significant signal overshoot and undershoot and oscillatory ringing. These factors can have an adverse effect on the detection process. Compared to the methods in U.S. Pat. Nos. 6,097,444 and 6,268,848, this scheme does utilize inter-phase relationship information. However, it requires dedicated hardware (such as ADCs) for each sampling phase, which can be expensive for many sampling phases.
The main limitations of the prior art circuits are thus imprecise, unreliable, or impractical determination of the sampling frequency and selection of the optimal sampling phase for reconstruction of an image for a digital display device. The prior art approaches use processes that employ test patterns, relies on imprecise clocks for digital to-analog conversion, compute with noisy data, ignore inter-phase relationships, and depend on signals with substantial overshoot and undershoot. A need thus exists for an apparatus and method to accurately determine the sampling frequency and to select the optimal sampling phase so that a digital image can be displayed that is not degraded by these limitations.